VHDL & FPGA

library ieee; use ieee.std_logic_1164.all; entity T_ff is generic ( n: integer; delay: time ); port ( t,clk : in std_logic; q : out std_logic); end T_ff; architecture mak of T_ff is signal data: std_logic; begin process(clk,t) begin if clk'event and clk = '1' then if t'last_event < delay then assert(t'last_event > delay) report "input duration was less" severity warning; else if t= '1' then data <= not data; end if; end if; end if; q <= data; end process; end mak;