VHDL & FPGA

سورس کد  مقایسه کننده ۴ بیتی  به زبان VHDL

تست شده

library ieee; use ieee.std_logic_1164.all; entity moghayese_4bit is port (a,b : in std_logic_vector( 3 downto 0 ); f : out std_logic); end moghayese_4bit; architecture mak of moghayese_4bit is signal d : std_logic_vector(3 downto 0); begin d(0)<= a(0) xnor b(0); d(1)<= a(1) xnor b(1); d(2)<= a(2) xnor b(2); d(3)<= a(3) xnor b(3); f <= d(0) and d(1) and d(2) and d(3) ; end mak;