VHDL & FPGA

سورس کد مبدل BCD به زبان VHDL

 تست شده

library ieee; use ieee.std_logic_1164.all; Entity bcd_7 is port ( A : in std_logic_vector( 3 downto 0); Sout: out std_logic_vector( 3 downto 0)); end bcd_7; architecture mak of bcd_7 is signal x: std_logic_vector ( 3 downto 0); signal c: std_logic_vector ( 3 downto 0); signal sel : std_logic; begin c(0) <= '0'; x(0) <= A(0) XOR '0' XOR C(0); C(1) <= (A(0) AND '0') OR ( '0' AND C(0)) OR ( A(0) AND C(0)); x(1) <= A(1) XOR '1' XOR C(1); C(2) <= (A(1) AND '1') OR ( '1' AND C(1)) OR ( A(1) AND C(1)); x(2) <= A(2) XOR '1' XOR C(2); C(3) <= (A(2) AND '1') OR ( '1' AND C(2)) OR ( A(2) AND C(2)); x(3) <= A(3) XOR '0' XOR C(3); sel <= (A(3) and A(1)) or (A(3) and A(2)); Sout <= A when (sel = '0') else x; END mak;